Power amplifiers are employed in a variety of devices. One class of such devices includes portable, battery-operated, devices, such as mobile telephones. Due to the restricted size and battery capacity of these mobile devices, the current consumption of such devices, and therefore the current consumption of each of the components of such devices, is strictly limited. Furthermore, as additional functions are being integrated into such mobile devices, more components share the limited battery capacity.
Typically, a power amplifier is one of the largest power consuming components of a mobile device, and in some devices such as some mobile telephones, the power amplifier operates full-time. Therefore, it is important that the power amplifier should have a high degree of efficiency, to conserve current consumption and extend the battery life. However, a conventional class AB power amplifier, which is generally used as a power amplifier in a mobile device, exhibits its maximum efficiency only in its maximum output power region. Therefore, many approaches have been tried to provide structures which enhance the efficiency of a power amplifier in low-power regions, but less investigation has been performed to find a way to enhance the efficiency at higher power levels.
Meanwhile, various commercial standards for mobile devices, such as CDMA, GSM, EDGE and WCDMA, each have their own maximum output power specifications. So it is very difficult to satisfy the efficiency requirement for devices complying with each of those standards by using a single power amplifier module. Therefore, a power amplifier in which is possible to modulate its output power level with maximum efficiency in the high power region is required in order to utilize a single power amplifier for several standard applications, as well as to enhance the efficiency and operation time of the mobile device.
Previous power amplifiers have divided their operating power usage into two or more regions in order to enhance the efficiency and achieve a longer operating time. However, because these devices modulate their power modes only either in a low or high power region, they have a limit to enhance power efficiency. Another disadvantage of the prior solutions is that RF switches typically have been utilized for mode switching, which increase performance degradation, structural complexity and production cost. Examples of some these approaches and a discussion of there limitations will now be provided as an illustration.
FIG. 1 is a functional block diagram of one embodiment of an amplification device 10. Amplification device 10 includes: a driver 100 for amplifying input power; a power stage 120 for receiving power amplified by the driver 100 through a first impedance matching unit 130 connected to the driver and a second impedance matching unit 140 connected to the first impedance matching unit 130, reamplifying the power and outputting the reamplified power; an applied voltage control circuit 90, connected to the power stage 120, for controlling applied voltages corresponding to the low power mode and the high power mode; an impedance transformer 170 for receiving power amplified by the driver 100 through the first impedance matching unit 130, according to operations of the applied voltage control circuit 90 and transferring the power to a fourth impedance matching unit 160; a third impedance matching unit 150, connected to the power stage 120 in serial, for transferring power amplified by the power stage 120 to the fourth impedance matching unit 160; and the fourth impedance matching unit 160, connected to the third impedance matching unit 150 and connected to impedance transformer 170, for transferring power, transferred from the third impedance matching unit 150 or impedance transformer 170, to an output stage 80 according to operations of the applied voltage control circuit 90.
Amplification device 10 provides two or three power modes so as to get increased power efficiency. Since the structure does not utilize any RF switches in the signal paths, little performance degradation is shown compared to other multiple power mode power amplifiers. The structure, however, operates at more than 10 dB backed off point from its maximum output power, and therefore power re-configurability and efficiency enhancement in a high power region from about 3 to 6 dB backed off from the maximum output power are not achievable.
FIG. 2 is a functional block diagram of another embodiment of an amplification device 20. Amplification device 20 includes: a switching mechanism 210 configured to receive an input signal (such as an RF input signal (“RF IN”)) at an input port 202 and to selectively route the input signal to either a first amplifier 220 or to a second amplifier 230 in response to a switch-control signal. In a first mode of operation selected by the switch-control signal, switching mechanism 210 routes the input signal to first amplifier 220; and, in a second mode of operation, switching mechanism 210 routes the input signal onto a bypass path to second amplifier 230. In either mode, the amplified signal is output at output port 206. In several of the disclosed embodiments, the first amplifier 220 is itself configured to operate in multiple power modes. First amplifier 220 includes matching network 272, preliminary amplifier 270, delay 266, low-power amplifier 240, high-power amplifier 242, impedance inverter 260, and matching network 274. Second amplifier 230 includes matching network 282 and ultra-low power amplifier 280.
Amplification device 20 has a discrete power mode in the higher power region. Despite its potential for enhancing efficiency in the higher power region, its complexity caused by the integration of RF switch 210 and complicated phase matching circuits make it hard to realize high productivity and low production costs.
FIG. 3 is a functional block diagram of yet another embodiment of an amplification device 30. Amplification device 30 includes an input network 310, output stages 330-1˜330-N, an output impedance matching network 350, an inter-stage matching network 382, and a bias-control network 370.
Amplification device 30 has discrete power modes for the high power region. However, it is difficult to optimize output matching circuit 350 for each of the respective power modes. Furthermore, by operating merely one of the output stages 330-1˜330-N for each power mode, the architecture essentially spends redundant chip area for inactivated output stages when it operates even at the highest power mode, which increases production cost for the device. In addition, since the circuit does not present a reasonable way to reduce current consumption in the low power region, it seems to have a restriction on its ability to enhance overall efficiency.
What is needed, therefore, is a power amplifier that can provide increased efficiency in both low power output regions, and also in high power output regions.